Estimation and Optimization of the Performance of Polyhedral Process Networks

Haastregt, S. van (2013)

Doctoral Thesis

A system-level design methodology such as Daedalus provides designers with a forward synthesis flow for automated design, programming, and implementation of multiprocessor systems-on-chip. Daedalus employs the polyhedral process network model of computation to represent applications. These networks are automatically derived from sequential C code. A forward synthesis flow greatly increases designer productivity. Still, the designer needs to perform a time-consuming forward synthesis step to learn if a network satisfies his performance constraints. Furthermore, it is not trivial to select a set of transformations and transformation parameters for a network such that performance requirements are met. A forward synthesis flow thus solves only part of a design problem, as it does not provide fast feedback on the transformations a designer should apply to meet his performance constraints. This dissertation intro duces different performance estimation techniques for polyhedral process networks. The most promising technique is the profiling-based cprof technique that works directly on the sequential application code. This makes cprof an easy-to-use, robust, and fast technique, without the need to derive a polyhedral process network. This dissertation then discusses four transformations and analyzes factors that affect the efficacy of each transformation.

• Polyhedral process networks
• Performance estimation
• System-level design
• Multiprocessor Systems-on-Chip (MPSoCs) design
• High-level synthesis

• All authors: Haastregt, S. van
• Supervisor: Deprettere, E.F.A
• Co-supervisor: Kienhuis, A.C.J.
• Qualification: Doctor (dr.)
• Awarding Institution: Leiden Institute of Advanced Computer Science (LIACS), Faculty of Sciences, Leiden University
• Date: 2013-12-17